module dipswreg
	(clock, resetn, DATAn, Q);
input			clock, resetn;
input	[3:0]	DATAn;
output	[3:0]	Q;

reg		[3:0]	Q;

always @(posedge clock or negedge resetn)
begin
	if (!resetn) Q <= 4'b0;
	else Q <= ~DATAn;
end
endmodule